UPMEM

dispositif informatique

N° FR3159453A1

DRAM MEMORY DEVICE USING A MECHANISM FOR ROW HAMMER MANAGEMENT

N° US2025124965A1

DRAM MEMORY DEVICE USING A MECHANISM FOR ROW HAMMER MANAGEMENT

N° WO2023104891A1

DRAM memory device using mechanisms for row hammer management

N° CN118339612A

MEMORY DEVICE AND METHOD FOR PROTECTING A MEMORY DEVICE FROM THE EFFECT OF ROW HAMMERING

N° WO2022207999A1

MEMORY DEVICE AND METHOD FOR PROTECTING A MEMORY DEVICE FROM THE EFFECT OF ROW HAMMERING

N° US2024185910A1

MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN SUCH A WAY AS TO MINIMIZE THE SIZE OF A MEMORY BLOCK ALLOWING MANAGEMENT OF THE ROW-HAMMERING

N° US2024135981A1

MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN A MODE THAT MINIMIZES MEMORY BLOCK SIZE TO ACCESS

N° CN117121106A

MEMORY DEVICE PROVIDED WITH DRAM MEMORY CIRCUITS ARRANGED IN SUCH A WAY AS TO MINIMISE THE SIZE OF A MEMORY BLOCK ALLOWING MANAGEMENT OF THE ROW-HAMMERING EFFECT

N° WO2022175619A1

행-해머링 효과를 관리할 수 있는 메모리 블록의 크기를 최소화하는 것과 같은 방식으로 배열된 DRAM 메모리 회로를 갖춘 메모리 디바이스

N° KR20230147646A

Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang

N° FR3130412A1

SEMICONDUCTOR DEVICE COMPRISING A STACK OF CHIPS, AND CHIPS FOR SUCH A STACK

N° US2023260968A1

SEMICONDUCTOR DEVICE COMPRISING A STACK OF CHIPS, AND CHIPS FOR SUCH A STACK

N° WO2022079381A1

Method and circuit for protecting DRAM memory device from ramming effect

N° CN116018645A

METHOD AND CIRCUIT FOR PROTECTING A DRAM MEMORY DEVICE FROM THE ROW HAMMER EFFECT

N° WO2021259593A1

로우 해머 효과로부터 DRAM 메모리 소자를 보호하는 방법 및 회로

N° KR20230026496A

dispositif mémoire DRAM configuré pour permettre une gestion d’un effet de martelage de rang d’une portée p supérieure ou égale à 2

N° FR3121261A1

Dispositif mémoire et procédé de protection d’un dispositif mémoire de l’effet de martelage d’un rang

N° FR3121262A1

Dispositif mémoire pourvu de circuits mémoire DRAM agences de manière à minimiser la taille d’un bloc mémoire permettant la gestion de l’effet de martelage de rang

N° FR3120153A1

Method and circuit for protecting a DRAM memory device from the row hammer effect

N° US2021398584A1

DISPOSITIF SEMI-CONDUCTEUR COMPRENANT UN EMPILEMENT DE PUCES ET PUCES D’UN TEL EMPILEMENT

N° FR3115395A1

Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang

N° FR3111730A1

Method and circuit for protecting a DRAM memory device from the row hammer effect

N° US10885966B1

Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang

N° FR3111731A1

집적 프로세서를 갖는 DRAM의 로우 해머 수정 로직

N° KR20200014805A

ROW HAMMER CORRECTION LOGIC FOR DRAM WITH INTEGRATED PROCESSOR

N° CN110741436A

ROW HAMMER CORRECTION LOGIC FOR DRAM WITH INTEGRATED PROCESSOR

N° WO2018215715A1

Row hammer correction logic for dram with integrated processor

N° US2021012832A1

METHODS AND DEVICES FOR BYPASSING INTERNAL CACHE OF ADVANCED DRAM MEMORY CONTROLLER

N° CN109952567A

진보한 DRAM 메모리 컨트롤러의 내부 캐시를 우회시키기 위한 방법 및 장치

N° KR20190067171A

Methods and devices for bypassing the internal cache of an advanced DRAM memory controller

N° US2021349826A1

METHODS AND DEVICES FOR BYPASSING THE INTERNAL CACHE OF AN ADVANCED DRAM MEMORY CONTROLLER

N° WO2018046850A1

LOGIQUE DE CORRECTION DE ROW HAMMER POUR DRAM AVEC PROCESSEUR INTEGRE

N° FR3066842A1

COMBINED INSTRUCTION FOR ADDITION AND CHECKING OF TERMINALS

N° CN108885548A

COMBINED INSTRUCTION FOR ADDITION AND CHECKING OF TERMINALS

N° WO2017137675A1

Combined instruction for addition and checking of terminals

N° US2019050223A1

IMPLEMENTATION OF AN ATOMIC OPERATION ON A MULTI-THREADED SINGLE-CORE PROCESSOR

N° WO2017055742A1

COMPUTER DEVICE PROVIDED WITH PROCESSING IN MEMORY AND NARROW ACCESS PORTS

N° EP3356945A1

Computer device provided with processing in memory and narrow access ports

N° CN108139989A

COMPUTER DEVICE PROVIDED WITH PROCESSING IN MEMORY AND NARROW ACCESS PORTS

N° WO2017055732A1

Computing device within memory processing and narrow data ports

N° US2018260161A1

METHODES ET DISPOSITIFS POUR CONTOURNER LE CACHE INTERNE D'UN CONTROLEUR MEMOIRE DRAM EVOLUE

N° FR3055715A1

Dram circuit provided with a built-in processor

N° CN107257964A

DRAM CIRCUIT PROVIDED WITH A BUILT-IN PROCESSOR

N° WO2016132052A1

Memory circuit with integrated processor

N° US2018039586A1

DRAM CIRCUIT PROVIDED WITH A BUILT-IN PROCESSOR

N° EP3259674A1

INSTRUCTION COMBINEE D'ADDITION ET DE VERIFICATION DE BORNES

N° FR3047577A1

DISPOSITIF INFORMATIQUE MUNI DE TRAITEMENT EN MEMOIRE ET DE PORTS D'ACCES ETROITS

N° FR3042050A1

MISE EN OEUVRE D'UNE OPERATION ATOMIQUE SUR UN PROCESSEUR MONO-COEUR MULTI-FILS

N° FR3042051A1

Brevet n°FR3042049A1

N° FR3042049A1

CIRCUIT DRAM MUNI D'UN PROCESSEUR INTEGRE

N° FR3032814A1